--1-- An exploration of synchronization solutions for parallel short-range optical interconnect in mesochronous systems Harald Devos
--2-- Introduction Optical links Synchronization Designs and simulations Conclusion
--3-- Introduction Bitrate of electrical interconnects limited by the aspect ratio *: * D.A.B. Miller and H.M. Ozaktas use of Optical Interconnects
--4-- Introduction long haul short haul
--5-- Introduction long haul short haul BW, bitrate also latency important
--6-- Introduction long haul short haul BW, bitrate also latency important high density, parallel
--7-- Introduction long haul short haul BW, bitrate also latency important high density, parallel mesochronous Synchronization needed
--8-- Introduction Optical links Synchronization Designs and simulations Conclusion
--9-- Optical links
Optical links latency IN OUT
Optical links eye-diagram
Optical links Jitter: HF, LF (wander) 2J T
Optical links Skew S T S
Optical links
Introduction Optical links Synchronization Designs and simulations Conclusion
Synchronization Synchronization = move data to the local clock domain Determine the phase Adjust the phase
Synchronization Adjusting the phase Clk Data Auxiliary Clk
Synchronization Adjusting the phase Clk Data Auxiliary Clk
Synchronization Adjusting the phase DQDQ Clk Data Auxiliary Clk ?
Synchronization Auxiliary clock: one of n clock phases Clk = C1 C1 C2 C3 C4 C5 T/5 e.g. n = 5
Synchronization Choice of auxiliary clock T/n T/2n T/n
Synchronization Parallel ? T/2-J-S T S T/2n
Introduction Optical links Synchronization Designs and simulations Conclusion
Designs Parallel Serial nn f f fff n.f n n Ref. Determine phase: use of a reference link
Designs AMS 0,6 µm – technology, standard libraries, state-of-the-art Different phase detection: 1. AJTI: ‘artificial jitter injection’ 2. Flip-flop phase detectors
Designs: AJTI Determine phase with AJTI Ref. …0101… 0101
Designs: AJTI Determine phase with AJTI Ref. …0101… 0101 AJTI
Designs: AJTI Determine phase with AJTI Ref. …0101…
Designs: AJTI Disadvantages Reference: not flexible Initialization Extra delay
Designs: FF phase detectors Determine phase with flip-flop phase detector Ref. ck ckQ Suited clock phases
Designs: FF phase detectors Advantages Flexibility reference signal –Data signal –PRBS –Serial word synchronization
Designs: comparison AJTI 2 or more clock phases Extra delay Initialisation problem Ref.=010101… FF phase detectors At least 4 clock phases Minimal delay Initialisation OK Ref.= signal with transitions
Designs Area and Power consumption
Introduction Optical links Synchronization Designs and simulations Conclusion
Conclusion If skew en jitter are sufficiently low, synchronization can be optimized Using an extra link can simplify the circuits Greater uniformity needed to minimize skew
Acknowledgments Joni Dambre, Wim Meeus, Dirk Stroobandt and Jan Van Campenhout
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Questions ? ?
--39--
Not mentioned Generation clock phases Influence of coding Comparison Synchronization circuits
Designs: flip-flop phase detector
Optical links Properties optical links: Latency Jitter Skew
Optical links Optical link
Optical links Soorten ontvangers: Transimpedantie versterker (TIA) - belangrijk statisch verbruik => verbruik per bit neemt af met stijgende frequentie
Optical links Soorten ontvangers: Geklokte versterker (sense-amplifier) - vooral dynamisch verbruik => verbruik per bit weinig afhankelijk van frequentie - zuiniger dan TIA - na bemonsteren geen ‘skew’ meer - klok nodig
Optical links Klok nodig Meezenden referentiesignaal extra kost extra voordeel Ook nuttig voor niet-geklokte ontvangers ?
Synchronization Mesochronous:
Designs: AJTI Voordelen,benefits profits: - Methode bruikbaar voor willekeurig aantal fasen
Designs: Gemeenschappelijke kenmerken Kost ~ 1/(# parallelle links) Hulpklok volgt fase bij drift Hulpklok: n e 1 e fase bit kwijt ! 1 e n e fase 2 maal zelfde bit!
Introduction Optical links Synchronization Designs and simulations Conclusion