1Ben Bruidegom Hoe rekent een computer II? Ben Bruidegom AMSTEL Instituut Universiteit van Amsterdam.

Presentatie over: "1Ben Bruidegom Hoe rekent een computer II? Ben Bruidegom AMSTEL Instituut Universiteit van Amsterdam."— Transcript van de presentatie:

1 1Ben Bruidegom Hoe rekent een computer II? Ben Bruidegom AMSTEL Instituut Universiteit van Amsterdam

2 2Ben Bruidegom Rekenen en rekenschakelingen Binaire code Hexadecimale code Optellen Two’s complement code Aftrekken Arithmetic Logic Unit Sign extension Look Ahead Carry Generation Vermenigvuldigen

3 3Ben Bruidegom Negatieve getallen One’s complement code 10001000.. 11001100 11011101 11101110 11111111 00000000 00010001 00100010 00110011 01110111 -7..-3-2-00123..7 Waarom is deze code minder geschikt?

4 4Ben Bruidegom Negatieve getallen Two’s complement code 10001000.. 11001100 11011101 11101110 11111111 00000000 00010001 00100010 00110011 01110111 -8..-4-3-20123..7 4-bit: Bereik -8.. +7

5 5Ben Bruidegom Negatieve getallen Hoe genereer ik een negatief getal?

6 6Ben Bruidegom Negatieve getallen Hoe genereer ik een negatief getal? getal0001 100125 complement1110 0110 1 Two’s complement1110 0111-25 Controle: -128 + 64 + 32 + 4 + 2 + 1 = -25

7 7Ben Bruidegom Negatieve getallen

8 8Ben Bruidegom 8 bit 0100 0000 = 64 1000 0111 = -121 Range: 0.. n = 8 Range –128.. 127 n = 16 Range -32768.. 32767 n = 32 Range –2.147.483.648.. 2.147.483.647 Signed Integer

9 9Ben Bruidegom Overflow (in 4 bit systeem) 1011 1010 -5 -6 10101+5 antwoord 1001 + overflow antwoord –7 + 16 = +9 0011 0110 3636 1001-7 ++ Negeren 4 bit systeem antwoord 0101 + overflow antwoord 5 - 16 = -11

10 10Ben Bruidegom Two’s complement code

11 11Ben Bruidegom Hoe werkt de hardware? Schakeling die kan aftrekken

12 12Ben Bruidegom Aftrekken : -3 – (+6) = -3 +(-6) 1101 0110 -3 6 - + Negeren 4 bit systeem antwoord 0111 + overflow antwoord 7 - 16 = -9 1101 1010 -3 -6 101117 0110 bits inverteren 1001 1 bij optellen 1 1010

13 13Ben Bruidegom 4 bits ALU

14 14Ben Bruidegom Overflow condities: Zie boek bladz. 172 Voor 16 bit systeem: Twee positieve getallen: antwoord negatief

15 15Ben Bruidegom Opgaven Opgaven: Hoofdstuk 4: Vervolg college: 10.30 uur De hierna behandelde sheets behoren niet tot de stof die voor AI-studenten is bestemd.

16 16Ben Bruidegom Arithmetic Logic Unit 32 operation result a b ALU

17 17Ben Bruidegom Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2 n -1 Of course it gets more complicated: numbers are finite (carry) fractions and real numbers negative numbers How do we represent negative numbers? i.e., which bit patterns will represent which numbers? Numbers

18 18Ben Bruidegom 0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten 0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten 0000 0000 0000 0000 0000 0000 0000 0010 two = + 2 ten... 0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten 0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0000 two = – 2,147,483,648 ten 1000 0000 0000 0000 0000 0000 0000 0001 two = – 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0010 two = – 2,147,483,646 ten... 1111 1111 1111 1111 1111 1111 1111 1101 two = – 3 ten 1111 1111 1111 1111 1111 1111 1111 1110 two = – 2 ten 1111 1111 1111 1111 1111 1111 1111 1111 two = – 1 ten maxint minint 32 bit signed numbers:

19 19Ben Bruidegom Converting n bit numbers into numbers with more than n bits:  MIPS 16 bit immediate gets converted to 32 bits for arithmetic  copy the most significant bit (the sign bit) into the other bits 0011 0010 -> 0000 0000 0011 0010 1001 1010 -> 1111 1111 1001 1010 "sign extension"

20 20Ben Bruidegom Conclusion We can build an ALU to support the MIPS instruction set  key idea: use multiplexor to select the output we want (fig. 2.7.1)  we can efficiently perform subtraction using two’s complement  we can replicate a 1-bit ALU to produce a 32-bit ALU Important points about hardware  all of the gates are always working  the speed of a gate is affected by the number of inputs to the gate???  the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) Our primary focus: comprehension, however,  Clever changes to organization can improve performance (similar to using better algorithms in software)  we’ll look at two examples for addition and multiplication

21 21Ben Bruidegom Is there more than one way to do addition? Is a 32-bit ALU as fast as a 1-bit ALU?  two extremes: ripple carry and sum-of-products c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 = = b 1 (b 0 c 0 + a 0 c 0 + a 0 b 0 )+ a 1 (b 0 c 0 + a 0 c 0 + a 0 b 0 )+ a 1 b 1 c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 c 3 = c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 c 4 = Not feasible! Why? Problem: ripple carry adder is slow

22 22Ben Bruidegom Can you see the ripple? How could you get rid of it?

23 23Ben Bruidegom An approach in-between our two extremes Motivation:  If we didn't know the value of carry-in, what could we do?  When would we always generate a carry? g i = a i. b i  When would we propagate the carry? p i = a i + b i Did we get rid of the ripple? c 1 = a 0.b 0 + b 0 c 0 + a 0 c 0 = a 0.b 0 + c 0 (b 0 +a 0 ) c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 c 2 = g 1 + p 1 (g 0 + p 0 c 0 ) c 3 = g 2 + p 2 c 2 c 3 = c 4 = g 3 + p 3 c 3 c 4 = Carry-lookahead adder

24 24Ben Bruidegom Use principle to build bigger adders

25 25Ben Bruidegom 1. Shift and ADD 2. Hardware Multiplication

26 26Ben Bruidegom Vermenigvuldigen op de basisschool 1101 0101 1101 00000 01101 110100 1000001 0000000 01000001

27 27Ben Bruidegom Multiplication: Shift and ADD Multiplier

28 28Ben Bruidegom Hardware vermenigvuldiger