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1CSNW1 Computersystemen en Netwerken Adrie van Doesburg Leo van Moergestel Jan Nijman  Wouter van Ooijen.

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Presentatie over: "1CSNW1 Computersystemen en Netwerken Adrie van Doesburg Leo van Moergestel Jan Nijman  Wouter van Ooijen."— Transcript van de presentatie:

1 1CSNW1 Computersystemen en Netwerken Adrie van Doesburg Leo van Moergestel Jan Nijman  Wouter van Ooijen

2 Cursusinformatie n Site: https://www.sharepoint.hu.nl/cursussen/fnt/TCTF-V1CSNW1-04 n Boek: Computersystemen en embedded systemen L.J.M. van Moergestel Academic Service ISBN

3 CSNW1 lesprogramma Week 1: Processors, bussystemen Week 2: Dataopslag Week 3: Datacommunicatie Week 4: Computernetwerken, ISO/OSI model Week 5: Ethernet Week 6: Internet Week 7: Inleiding Operating Systems proeftentamen

4 PU(s) MEMORY I/O Adresbus databus besturingsbus Computersysteem (herh.)

5 IF ID EX Exception Cycle Von Neumann cyclus (herh.)

6 Registers ALU Status register Stack pointer PC controle unit Instruction register memory and I/O Von Neumann machine (herh.)

7

8 Konrad Zuse's First Computer The Z1 (1936, relais) Bron:

9 The Chip that Jack Built Changed the World Integrated circuit Jack Kilby (JK-Flip/Flop) 1959, TI Bron:

10 Intel: 4004 Processor 2300 Transistoren 10 um technologie 0,108 MHz Ted Hoff Microprocessor (Intel 1971) Bron: /www.intel.com/museum/archives/4004.htm

11 Core 2 Duo (Intel 2006) n Core 2 Duo n 291M transistoren n 65 nm technologie n 1-3,3 GHz Bron:

12 RISC versus CISC n Complex instruction set computer (CISC): n many addressing modes; n complex operations. n Reduced instruction set computer (RISC): n load/store; n simple operations n pipelinable instructions.

13 n De instructies verrichten simpele taken n Alle instructies zijn even groot n Er is geen uitgebreide keuze aan adresseer- modes n Er zijn veel interne registers beschikbaar n Load and Store architecture RISC

14 Pipelining

15 Superscalaire instructieafhandeling

16 Super Pipelining

17 Super Pipelining (2)

18 Kenmerken Processoren n Architectuur n Programmeermodel n Instructieset n Technologie (fabricage)

19 ARM Processor Architecture

20 Core 2 Duo Architecture Bron:

21 Cell Processor Architecture (Sony Playstation 3) Bron: H.P. Hofstee

22 Programmeermodellen

23 Instructieset (herh.) Verplaatsing (mov, ldr, str) n Bewerking Logisch (and, or, lsl, … ) Rekenkundig (add, sub, mul, … ) n Sprong Conditioneel (beq, bne, … ) Niet conditioneel (jmp, bra, … ) Subroutine aanroep (call, ret, …) Speciale instructies (nop, hlt, swi, … )

24

25 Bus hierarchie

26 Timing: Asynchrone Bus

27 Timing: Synchrone Bus

28 PCI gebaseerd computersysteem

29 PCI-bus Burst Transfer

30 Accellerated Graphics Port (AGP)

31 Intel PM855 Chipset Bron:

32 PCI Express Based System Bron: AV Bhatt, Intel

33 PCI Express Lanes Bron: AV Bhatt, Intel

34 PCI Express Layers Bron: AV Bhatt, Intel

35 USB Architectuur

36 USB Hubs

37 A Low Speed rate of 1.5 Mbits/sec that is mostly used for Human Interface Devices (HID) such as keyboards, mice and joysticks. A Full Speed rate of 12 Mbit/s. A Hi-Speed rate of 480 Mbit/s. Plug and play Hot swap Power supply 5 V, 500 mA USB signals are transmitted on a twisted pair of data cables, labelled D+ and D−. These collectively use half-duplex differential signalling. Transmitted signal levels are 0.0–0.3 V for low and 2.8–3.6 V for high. Universal Serial Bus (USB)

38 Practicum - ZEP2 Simulator

39 Links n CPU (Wikipedia) CPU (Wikipedia) n Intel Processors Site Intel Processors Site n SIMD (Wikipedia) SIMD (Wikipedia) n DSP (Wikipedia) DSP (Wikipedia) n Computer Bus (Wikipedia) Computer Bus (Wikipedia) n PCI-bus (Wikipedia) PCI-bus (Wikipedia) n PCI Express (Wikipedia) PCI Express (Wikipedia) n USB in a Nutshell USB in a Nutshell n Firewire (Wikipedia) Firewire (Wikipedia)

40 Opdrachten n Bestudeer 8.1 t/m 8.3 en 8.6 n Lees PCI-express whitepaper n Maak opgaven 8.1 t/m 8.5


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