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Computersystemen en Netwerken

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Presentatie over: "Computersystemen en Netwerken"— Transcript van de presentatie:

1 Computersystemen en Netwerken
1CSNW1 Computersystemen en Netwerken Adrie van Doesburg Leo van Moergestel Jan Nijman  Wouter van Ooijen

2 Cursusinformatie Site: https://www.sharepoint.hu.nl/cursussen/fnt/TCTF-V1CSNW1-04 Boek: Computersystemen en embedded systemen L.J.M. van Moergestel Academic Service ISBN

3 CSNW1 lesprogramma Week 1: Processors, bussystemen Week 2: Dataopslag
Week 3: Datacommunicatie Week 4: Computernetwerken, ISO/OSI model Week 5: Ethernet Week 6: Internet Week 7: Inleiding Operating Systems proeftentamen

4 Computersysteem (herh.)
PU(s) MEMORY I/O Adresbus databus besturingsbus

5 Von Neumann cyclus (herh.)
Exception Cycle IF ID EX

6 Von Neumann machine (herh.)
Registers ALU Status register Stack pointer PC controle unit Instruction register memory and I/O

7 xxxxxxxxxxxxxxx 4/4/2017 Processoren xxxxxxxxxxxxx

8 Konrad Zuse's First Computer The Z1 (1936, relais)
Bron:

9 Integrated circuit Jack Kilby (JK-Flip/Flop) 1959, TI
The Chip that Jack Built Changed the World Bron:

10 Microprocessor (Intel 1971)
Ted Hoff Intel: 4004 Processor 2300 Transistoren 10 um technologie 0,108 MHz Bron: /www.intel.com/museum/archives/4004.htm

11 Core 2 Duo (Intel 2006) Core 2 Duo 291M transistoren 65 nm technologie
1-3,3 GHz Bron:

12 RISC versus CISC Complex instruction set computer (CISC):
many addressing modes; complex operations. Reduced instruction set computer (RISC): load/store; simple operations pipelinable instructions.

13 RISC De instructies verrichten simpele taken
Alle instructies zijn even groot Er is geen uitgebreide keuze aan adresseer-modes Er zijn veel interne registers beschikbaar Load and Store architecture

14 Pipelining

15 Superscalaire instructieafhandeling

16 Super Pipelining

17 Super Pipelining (2)

18 Kenmerken Processoren
Architectuur Programmeermodel Instructieset Technologie (fabricage)

19 ARM Processor Architecture

20 Core 2 Duo Architecture Bron:

21 Cell Processor Architecture (Sony Playstation 3)
Bron: H.P. Hofstee

22 Programmeermodellen

23 Instructieset (herh.) Verplaatsing (mov, ldr, str) Bewerking Sprong
Logisch (and, or, lsl, … ) Rekenkundig (add, sub, mul, … ) Sprong Conditioneel (beq, bne, … ) Niet conditioneel (jmp, bra, … ) Subroutine aanroep (call, ret, …) Speciale instructies (nop, hlt, swi, … )

24 xxxxxxxxxxxxxxx 4/4/2017 Bussystemen xxxxxxxxxxxxx

25 Bus hierarchie

26 Timing: Asynchrone Bus

27 Timing: Synchrone Bus

28 PCI gebaseerd computersysteem

29 PCI-bus Burst Transfer

30 Accellerated Graphics Port (AGP)

31 Intel PM855 Chipset Bron:

32 PCI Express Based System
Bron: AV Bhatt, Intel

33 PCI Express Lanes Bron: AV Bhatt, Intel

34 PCI Express Layers Bron: AV Bhatt, Intel

35 USB Architectuur

36 USB Hubs

37 Universal Serial Bus (USB)
A Low Speed rate of 1.5 Mbits/sec that is mostly used for Human Interface Devices (HID) such as keyboards, mice and joysticks. A Full Speed rate of 12 Mbit/s. A Hi-Speed rate of 480 Mbit/s. Plug and play Hot swap Power supply 5 V, 500 mA USB signals are transmitted on a twisted pair of data cables, labelled D+ and D−. These collectively use half-duplex differential signalling. Transmitted signal levels are 0.0–0.3 V for low and 2.8–3.6 V for high.

38 Practicum - ZEP2 Simulator

39 Links CPU (Wikipedia) Intel Processors Site SIMD (Wikipedia)
DSP (Wikipedia) Computer Bus (Wikipedia) PCI-bus (Wikipedia) PCI Express (Wikipedia) USB in a Nutshell Firewire (Wikipedia)

40 Opdrachten Bestudeer 8.1 t/m 8.3 en 8.6 Lees PCI-express whitepaper
Maak opgaven 8.1 t/m 8.5


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