Computersystemen en Netwerken 1CSNW1 Computersystemen en Netwerken Adrie van Doesburg Leo van Moergestel Jan Nijman  Wouter van Ooijen

Cursusinformatie Site: https://www.sharepoint.hu.nl/cursussen/fnt/TCTF-V1CSNW1-04 http://wwwvoti.nl/hvu/V1CSNW1 Boek: Computersystemen en embedded systemen L.J.M. van Moergestel Academic Service ISBN 978-90-395-2528-9

CSNW1 lesprogramma Week 1: Processors, bussystemen Week 2: Dataopslag Week 3: Datacommunicatie Week 4: Computernetwerken, ISO/OSI model Week 5: Ethernet Week 6: Internet Week 7: Inleiding Operating Systems proeftentamen

Computersysteem (herh.) PU(s) MEMORY I/O Adresbus databus besturingsbus

Von Neumann cyclus (herh.) Exception Cycle IF ID EX

Von Neumann machine (herh.) Registers 1001001001001110 ALU Status register Stack pointer PC controle unit Instruction register 1001101101100011 0011100101111010 memory and I/O

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Konrad Zuse's First Computer The Z1 (1936, relais) Bron: www.epemag.com/zuse

Integrated circuit Jack Kilby (JK-Flip/Flop) 1959, TI The Chip that Jack Built Changed the World Bron: www.ti.com/corp/docs/kilbyctr/jackbuilt.shtml

Microprocessor (Intel 1971) Ted Hoff Intel: 4004 Processor 2300 Transistoren 10 um technologie 0,108 MHz Bron: /www.intel.com/museum/archives/4004.htm

Core 2 Duo (Intel 2006) Core 2 Duo 291M transistoren 65 nm technologie 1-3,3 GHz Bron: www.intel.com

RISC versus CISC Complex instruction set computer (CISC): many addressing modes; complex operations. Reduced instruction set computer (RISC): load/store; simple operations pipelinable instructions.

RISC De instructies verrichten simpele taken Alle instructies zijn even groot Er is geen uitgebreide keuze aan adresseer-modes Er zijn veel interne registers beschikbaar Load and Store architecture

Pipelining

Superscalaire instructieafhandeling

Super Pipelining

Super Pipelining (2)

Kenmerken Processoren Architectuur Programmeermodel Instructieset Technologie (fabricage)

ARM Processor Architecture

Core 2 Duo Architecture Bron: www.zdnet.com.au

Cell Processor Architecture (Sony Playstation 3) Bron: H.P. Hofstee

Programmeermodellen

Instructieset (herh.) Verplaatsing (mov, ldr, str) Bewerking Sprong Logisch (and, or, lsl, … ) Rekenkundig (add, sub, mul, … ) Sprong Conditioneel (beq, bne, … ) Niet conditioneel (jmp, bra, … ) Subroutine aanroep (call, ret, …) Speciale instructies (nop, hlt, swi, … )

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Bus hierarchie

Timing: Asynchrone Bus

Timing: Synchrone Bus

PCI gebaseerd computersysteem

PCI-bus Burst Transfer

Accellerated Graphics Port (AGP)

Intel PM855 Chipset Bron: www.intel.com

PCI Express Based System Bron: AV Bhatt, Intel

PCI Express Lanes Bron: AV Bhatt, Intel

PCI Express Layers Bron: AV Bhatt, Intel

USB Architectuur

USB Hubs

Universal Serial Bus (USB) A Low Speed rate of 1.5 Mbits/sec that is mostly used for Human Interface Devices (HID) such as keyboards, mice and joysticks. A Full Speed rate of 12 Mbit/s. A Hi-Speed rate of 480 Mbit/s. Plug and play Hot swap Power supply 5 V, 500 mA USB signals are transmitted on a twisted pair of data cables, labelled D+ and D−. These collectively use half-duplex differential signalling. Transmitted signal levels are 0.0–0.3 V for low and 2.8–3.6 V for high.

Practicum - ZEP2 Simulator

Links CPU (Wikipedia) Intel Processors Site SIMD (Wikipedia) DSP (Wikipedia) Computer Bus (Wikipedia) PCI-bus (Wikipedia) PCI Express (Wikipedia) USB in a Nutshell Firewire (Wikipedia)

Opdrachten Bestudeer 8.1 t/m 8.3 en 8.6 Lees PCI-express whitepaper Maak opgaven 8.1 t/m 8.5